1. Field of the Invention
The present invention relates to VLSI semiconductor devices and, particularly to the formation of a gate electrode of a field effect transistor (FET) having a reduced signal propagation time at the gate electrode.
2. Description of the Related Art
The manufacturing process of integrated circuits (ICs) involves the fabrication of numerous semiconductor devices, such as insulated gate field effect transistors, on a single substrate. In order to provide increased integration density and improved device performance, for instance with respect to signal processing time and power consumption, feature sizes of the semiconductor devices are steadily decreasing. In general, decreasing features sizes of an FET provide a variety of advantages, such as high package density and small rise and fall times during switching of the transistors due to the reduced channel length. On the other hand, the reduced gate length of the FET may lead to certain disadvantages that offset the advantage associated with the smaller channel length, since the gate resistance and, thus, signal delay of the gate electrode increases as the gate length decreases.
To clearly demonstrate the problems involved with steadily decreasing feature sizes of modem ultra-high density integrated circuits, a typical prior art process flow will be described with reference to FIGS. 1a-1d, in which particularly the problems involved with the formation of the gate electrode and the gate electrode contact are detailed. As the skilled person will readily appreciate, the figures depicting the prior art processing are merely of a schematic nature, and transitions and boundaries illustrated as sharp lines may not be imparted as sharp transitions in a real device. Furthermore, the description of the typical prior art process refers to standard manufacturing procedures without specifying typical process parameter values used for these procedures, since individual processing steps may be accordingly adapted to meet specific design requirements.
FIG. 1a shows a schematic cross-sectional view of an FET device at a specific manufacturing stage. In a semiconductor substrate 101, such as a silicon substrate, a transistor active region comprising drain and source regions 105 separated by a channel 108 is defined by shallow trench isolations 102. Over the channel 108, a gate electrode 104 is formed and separated from the channel by a gate insulation layer 103. The sidewalls of the gate electrode 104 are covered by sidewall spacers 107. On top of the drain and source regions 105 and the gate electrode 104, cobalt silicide portions 106 are provided. The drain and source regions 105 and the gate electrode 104 extend substantially in a parallel manner along a transistor width direction which is perpendicular to the drawing plane of FIG. 1a. In FIG. 1a, the horizontal direction is referred to as the xe2x80x9ctransistor length dimension,xe2x80x9d and the lateral extension of the gate electrode 104 is called the xe2x80x9cgate length.xe2x80x9d
As the skilled person will readily appreciate, formation of the structure shown in FIG. 1a may comprise the following steps: forming the shallow trench isolations 102 which consist of, for example, silicon dioxide, depositing or growing a gate insulation layer, depositing a gate electrode material, such as polycrystalline silicon, and patterning the gate electrode material by, for instance, deep ultraviolet photolithography and etching, creating lightly doped drain and source regions and lightly doped out-diffused regions by ion implantation and subsequent rapid thermal annealing, forming the sidewall spacers 107 to subsequently perform a further implantation step to obtain the drain and source regions 105, and depositing a metal, such as cobalt, to initiate a chemical reaction between the silicon surfaces of the drain and source regions 105 and the gate electrode 104. The thereby obtained silicide portions 106 exhibit a sheet resistance of about 10 ohm/square.
FIG. 1b schematically shows a cross-sectional view of the device of FIG. 1a in an advanced manufacturing stage. In a dielectric layer 109 having a planarized surface, drain and source contacts 110 are formed which are partially in contact with the drain and source regions 105, respectively, via cobalt silicide portions 106. The drain and source contacts 110 comprise a barrier layer 111 in contact with the dielectric layer 109 and the silicide portions 106 of the drain and source regions 105. Typically, formation of the structure shown in FIG. 1b is accomplished by depositing a dielectric material, such as silicon dioxide, and polishing back the deposited material to yield a planar surface. Thereafter, contact openings are patterned, etched and subsequently filled with a barrier metal forming the barrier layer 111 and a contact metal such as tungsten. Next, the excess metal is removed by chemical mechanical polishing, as is well known in the art, to thereby obtain drain and source contacts 110.
FIG. 1c schematically shows the device of FIGS. 1a and 1b in a final stage. In a second dielectric layer 113, openings are formed which are filled with a second metal, such as aluminum, for providing metal lines 114. The second dielectric layer 113 may be comprised of silicon dioxide or an appropriate dielectric material having a low dielectric constant.
FIG. 1d schematically shows a top view of the device of FIG. 1c, wherein, for the sake of simplicity, the metal lines 114, the second dielectric layer 113, the dielectric layer 109, and the silicide portions 106 are not shown. In FIG. 1d, the drain region and the source region, respectively, are contacted by three contacts 110, whereas the gate electrode 104 is connected to two gate electrode contacts 112 that are located outside the transistor active region. From FIG. 1d it is obvious that a gate voltage applied to the contacts 112 is supplied to the gate electrode via the relatively high-ohmic silicide portion 106 of the gate electrode. Hence, the creation of a conductive channel between the drain region and the source region, in case of an enhancement type FET, upon applying a voltage to the gate contacts 112 is significantly delayed due to the high gate resistance. This situation becomes even worse when the size of the gate electrode, e.g., the gate length, is reduced, as required for optimization of the DC properties of the transistor, since the reduced gate cross-section further increases the gate resistance, and thus partially offsets the advantage obtained by the reduced channel length. Accordingly, improved DC transistor characteristics obtained by a reduced channel length do not necessarily result in a corresponding improved AC performance of the transistor.
In view of the above, there exists a need for an improved FET device having lower gate delay to enhance the AC performance of the transistor.
According to one aspect of the present invention, a field effect transistor formed on a substrate comprises a drain region and a source region, spaced apart from each other in a transistor length dimension by a channel region, a gate electrode formed over the channel and insulated therefrom by a gate insulation layer, the drain region, the source region, and the gate electrode extending substantially in a parallel manner along a transistor width dimension. The field effect transistor further comprises a drain contact at least partially formed over the drain region and comprising a metal, wherein the drain contact connects the drain region to a drain metallization line, a source contact at least partially formed over the source region and comprising a metal, the source contact connecting the source region to a source metallization line, and a gate contact at least partially formed over and in contact with the gate electrode and comprising an electrically conductive material, wherein the gate contact has a width extension along the gate electrode in the transistor width dimension that covers the gate electrode at least along a portion of the channel region, thereby providing a reduced gate electrode resistance.
The transistor device in accordance with the present invention has a gate contact that is at least partially formed over the channel of the transistor. Accordingly, due to the significantly increased cross-section of electric conductive material, the resulting electrical resistance of the gate electrode is significantly reduced when compared to a prior art device in which polysilicon end caps are formed outside of the transistor active region. Thus, a transistor device in accordance with the present invention drastically reduces signal delay, and hence contributes to an improved AC performance of the transistor device as required in modem integrated circuits, such as microprocessors and the like, where the field effect transistors are operated at clock frequencies of 1 GHz and higher.
In a further embodiment, the gate contact extends along the entire width of the channel so that signal propagation time at the gate electrode is decreased even more. Moreover, the gate electrode contact may additionally comprise a gate metallization line that is formed over the gate contact, which additionally reduces the effective gate electrode resistance. The length dimension of the gate contact and/or the gate metallization line may exceed the length of the gate electrode so as to obtain a large, effective cross-section for charge carrier transportation along the width direction of the gate electrode, thereby further decreasing the effective electrical resistance.
According to another aspect of the present invention, a method of forming a transistor having a length direction and a width direction comprises forming a gate insulation layer above an active region of a semiconducting substrate, forming a gate electrode above the gate insulation layer, and forming a source region and a drain region in the active region adjacent the gate electrode. The method further comprises forming a gate contact above the gate electrode, wherein the gate contact is electrically coupled to the gate electrode and extends, in a transistor width direction, above at least a portion of the active region.
The method according to the present invention allows the formation of a field effect transistor having the advantages as pointed out above. Moreover, the process steps involved in performing the method are compatible with standard semiconductor manufacturing procedures so that the method may be implemented in a process line without undue re-organization of the process flow.